In recent years, semiconductor integrated circuits (large-scale integrated circuit: LSI) used in electronic equipment have had higher packing density and higher degree of integration. With such trend, LSI chips having higher-pin-count, finer-pitch connection terminals are rapidly developed. For packaging of these LSI chips onto a wiring substrate, flip-chip packaging is widely used in order to reduce wiring delay. Generally, in the flip-chip packaging, a solder bump is formed on a connection terminal in an LSI chip, and the chip is collectively connected through the solder bump to an electrode terminal formed on a wiring substrate.
However, in order to package onto the wiring substrate the next-generation LSI having connection terminals as great as 5000 or more, it is necessary to form bumps adaptable to a fine pitch design less than 100 μm, but a currently used solder bump formation technology is difficult to adapt to such design. Moreover, a great number of bumps according to the number of connection terminals have to be formed therein. Therefore, in order to reduce production costs, high productivity of devices attained by cutting the mounting time per chip is also demanded.
Conventionally, as a bump formation technique, for example, a plating method or a screen printing method has been developed. The plating method is suited for fine-pitch design, but it has a problem with productivity due to its complicated process. On the other hand, the screen printing method excels in productivity, but it is not suited to fine-pitch design due to use of masks.
In light of such current circumstances, some techniques for selectively forming solder bumps on electrodes on an LSI chip or a wiring substrate have been recently developed. These techniques are suited for formation of fine bumps. In addition to this, these techniques can collectively form bumps, so that they also excel in productivity. Therefore, they are attracting attention as a technique adaptable to packaging of a next-generation LSI onto a wiring substrate.
One of these techniques is disclosed in, for example, Patent Document 1. In this technique, solder paste made of a mixture of solder powder and flux is applied entirely over a substrate formed at its surface with an electrode, and the resulting substrate is heated to melt the solder powder, thereby selectively forming a solder bump on the electrode having high wettability.
For example, in a technique disclosed in Patent Document 2, composite paste (chemical deposition type solder) mainly containing lead salt of organic acid and metal tin is applied entirely over a substrate formed with an electrode and the resulting substrate is heated to cause substitution reaction of Pb and Sn, thereby selectively depositing Pb/Sn alloy on the electrode of the substrate.
The solder formation technique disclosed in Patent Document 1, however, is intended to prevent a short circuit between adjusting terminals and also provide an appropriate wettability for metal by controlling surface oxidation of solder powder. However, it is difficult to control the essentially contradictory properties only by the oxidation amount and the oxidation method. In addition, since the material for the chemical deposition type solder used in Patent Document 2 is prepared by utilizing a specific chemical reaction, the flexibility in selection of solder composition is low. Therefore, it still has a problem in handling of Pb-free solder.
In the conventional flip-chip packaging employing a bump formation technique, a semiconductor chip is mounted to a wiring substrate formed with a bump. Then, in order to fix the semiconductor chip to the wiring substrate, the process of injecting a resin called an underfill into a space between the semiconductor chip and the wiring substrate is additionally required.
From the circumstances described above, a flip-chip packaging technique (see, for example, Patent Document 3) using an anisotropic conductive material is developed as a method for simultaneously making an electrical connection between the semiconductor chip and opposed electrode terminals of the wiring substrate and fixing the semiconductor chip to the wiring substrate. In this technique, thermosetting resin having conductive particles contained therein is supplied to a space between the wiring substrate and the semiconductor chip, and then pressurization of the semiconductor chip and heating of the thermosetting resin are simultaneously performed to simultaneously make an electrical connection between the semiconductor chip and the electrode terminals of the wiring substrate and fix the semiconductor chip to the wiring substrate.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-94179
[Patent Document 2] Japanese Unexamined Patent Publication No. H1-157796
[Patent Document 3] Japanese Unexamined Patent Publication No. 2000-332055